The present invention relates to via and trench metallization in an integrated circuit. More particularly, the present invention relates to a simplified introduction, patterning, and formation of multiple-layer interconnections in a semiconductor structure.
Integrated circuits use conductive contacts and interconnects to wire together the individual devices on a semiconductor substrate, or to communicate external to the integrated circuit. Interconnect metallization for vias and trenches may include aluminum alloys and copper. A typical method of forming an interconnect is a damascene process that involves forming a via recess and an overlying trench recess in a dielectric material. The via recess and the trench recess (hereinafter referred to as xe2x80x9crecessxe2x80x9d) is lined with a barrier layer. Where deposition assistance is required, a conductive seed material is deposited in the recess. Interconnect material is introduced into the recess, the semiconductor structure may be planarized, and a dielectric material may be formed over the interconnect.
Copper has recently been introduced as an interconnect material. But copper has technical challenges such as poor adherence to dielectrics and the resulting electromigration by the copper material during device use. Another problem for copper is poor recess fill properties that result in voids. Additionally, of copper may blister or form hillocks during thermal processing.
As integrated circuits become more complex, process integration requires several processes such as forming etch stop and diffusion barrier layers in the interlayer dielectrics that surround interconnect. Additionally, because the real estate of a semiconductor device is subject to miniaturization, often multi-level interconnects are required. Typically, metallizations may be numbered, such as metal-one (M1) up to and exceeding metal-six (M6). With copper, the requirement of several layers of metallization becomes increasingly complicated by the associated requirement of etch stop and diffusion barrier structures at each level. Further, a high-density interconnect layout can require vias that do not fully land on the underlying metal layer. Unlanded vias may have significantly reduced electrical connection to the lower metallization that will result in both process yield lowering and in field failures.